- MOS Technology 6502
- Mouser Sells Classic 6502 "Antique" Processor
- Motorola 6800
- MOS Technology 6502
- Motorola 6809
MOS Technology 6502After studying up on the architecture of all these different CPUs, I decided that the was still the best choice to use as a model, because I believe it can be implemented using the least CPLD resources. The cross-CPU comparisons were very interesting. The key differences between these early 8-bit CPUs fell into four main areas: number of data registers, bit instruction support, address registers, indexed addressing. While all the CPUs in this group are 8-bit designs, some support a limited number of bit operations too. These are very handy for the programmer, but any bit operation can also be performed as a series of 8-bit operations, so the difference is one of speed and not capability. Most modern CPUs store an address in a user-visible register, then use other instructions to manipulate the data at that address. For example, the and have the M register, which can hold a bit address. This is convenient, because you can do things like perform arithmetic on M in order to construct the right address for a value in a struct. Another way of approaching addresses is to include them directly in the instruction itself. A CPU that supports absolute addresses directly in the instruction must have a hidden, temporary address register. That address in the program code has to be loaded somewhere, so that it can then drive the address bus, and a user-hidden address register fits the bill nicely. Having only a user-visible address register creates a fairly clunky programming experience, because it rules out having absolute addresses in the instruction, and forces the programmer to manually load the address register first before every memory reference. This is what the does. Most CPUs have both. The is unique in this group by having only a hidden address register, and no user-visible one. This gives up some flexibility, but is still a workable solution and eliminates one large register from the CPLD. A very common pattern in assembly language programming is to reference a memory location using a combination of a base address and an offset. When performing some operation to many consecutive memory locations, this is generally faster and more convenient than altering the base pointer each time through the loop. Not all those early 8-bit CPUs supported indexed addressing. The supports indexed addressing in the most resource-efficient manner of the CPUs in this group. I had a lot of fun programming the when I was younger. It can actually do a little more than you describe. The U register can be used just like X and Y for example, indexed addressingbut it also can be used as a secondary stack pointer. At the other extreme, if you are willing to do without any stack, the S stack pointer register can be used exactly like X and Y as well. For the indexed addressing modes, the offset was signed and could be 0, 5, 8, or 16 bits in size the different formats allowed more common cases to fit into as small of an instruction as possible and you could use X, Y, U, or S. The offset could also come from the accumulator registers A, B, or D. Indexed addressing mode with the stack pointer S made using local variables kept on the stack trivial. You could also index using an 8 or 16 bit signed offset relative to the program counter. Using the indexed addressing modes with the load effective address instruction, you could easily do bit addition and subtraction. So examples:. The could do something like that with its Y register too, I think. The fancier indexed addressing modes do come at the expense of longer and more complicated instructions to decode so I agree that the is probably a better source of inspiration for you CPLD CPU. Cool, sounds like the was pretty advanced for its time. Too bad it never caught on very widely. Neat, huh? Also, IX and IY are just what the doctor ordered for referencing fields of data structures, which was their original intent. One thing I wish this little CPU survey had addressed is support for position-independent code. On a the only purely relative addressing is found in the branch instructions, which include a signed 8-bit displacement that gets added to the PC if the branch is taken; all other instructions barring the register-only stuff like operations using immediate data, index-register increments, and register-to-register transfers require at least one memory address to be hard-coded in the instruction. Can anyone comment on how the other five CPUs considered here stack up in this regard?
Mouser Sells Classic 6502 "Antique" Processor
The " sixty-eight hundred " is an 8-bit microprocessor designed and first manufactured by Motorola in A significant design feature was that the M family of ICs required only a single five-volt power supply at a time when most other microprocessors required three voltages. The M Microcomputer System was announced in March and was in full production by the end of that year. It has 72 instructions with seven addressing modes for a total of opcodes. In addition to the ICs, Motorola also provided a complete assembly language development system. The customer could use the software on a remote timeshare computer or on an in-house minicomputer system. An expansive documentation package included datasheets on all ICs, two assembly language programming manuals, and a page application manual that showed how to design a point-of-sale computer terminal. The was popular in computer peripheralstest equipment applications and point-of-sale terminals. It also found use in arcade games  and pinball machines. Galvin Manufacturing Corporation was founded in ; the company name was changed to Motorola in Motorola's transistors and integrated circuits were used in-house for their communication, military, automotive and consumer products and they were also sold to other companies. In the early s Motorola started a project that developed their first microprocessor, the MC This was followed by single-chip microcontrollers such as the MC and MC Motorola did not chronicle the development of the microprocessor the way that Intel did for their microprocessors. In the Computer History Museum interviewed four members of the microprocessor design team. Their recollections can be confirmed and expanded by magazine and journal articles written at the time. By the time the project was finished, Bennett had 17 chip designers and layout people working on five chips. LaVell had 15 to 20 system engineers and there was another applications engineering group of similar size. Tom Bennett had a background in industrial controls and had worked for Victor Comptometer in the s designing the first electronic calculator to use MOS ICs, the Victor Bennett joined Motorola in to design calculator ICs. He was soon assigned as the chief architect of the microprocessor project that produced the In September Robert H. Cushman then asked "Tom Bennett, master architect of the ", to comment about this new competitor. Jeff LaVell joined Motorola in and worked in the computer industry marketing organization. They would study the customer's products and try to identify functions that could be implemented in larger integrated circuits at a lower cost. The result of the survey was a family of 15 building blocks; each could be implemented in an integrated circuit. John Buchanan was a memory designer at Motorola when Bennett asked him to design a voltage doubler for the It was easy to eliminate the -5 volt supply but the MOS transistors needed a supply of 10 to 12 volts. This on-chip voltage doubler would supply the higher voltage and Buchanan did the circuit design, analysis and layout for the microprocessor. He received patents on the voltage doubler and the chip layout. Later Orgill would design the MOS Technology microprocessor that was socket compatible with the Bill Lattin joined Motorola in and his group provided the computer simulation tools for characterizing the new MOS circuits in the Bill Mensch joined Motorola in after graduating from the University of Arizona. He had worked several years as an electronics technician before earning his BSEE degree. The first year at Motorola was a series of three-month rotations through four different areas.
The had 46 instructions, using only 2, transistors in a pin DIP. It ran at a clock rate of kHz eight clock cycles per CPU cycle of The was an enhanced version of theadding 14 instructions, larger 8 level stack, 8K program space, and interrupt abilities including shadows of the first 8 registers. Should Pioneer 10 and Pioneer 11 ever be found by an extraterrestrial species, the will represent an example of Earth's technology. S Navy qualifies as the "first microprocessor". Although interesting, it was not a single-chip processor, and was not general purpose - it was more like a set of parallel building blocks you could use to make a special purpose digital signal processor from in the form of one or more data pipelines in parallel. It's only included here because at least two people asked me about it. It was bit serial to reduce connections between chips, with highly parallel design and high clock rate to compensate. Words were 20 bits required by the precision of the sensor and control values and ALU units could perform operations on input bits as they were read in, while bits of the previous result was read out. Bits read serially from the ROMS eight banks with bit words, each with its own program counter directed the data movement and unit operations, but had to be synchronized with data movement making programming difficult basically microcode. Programming consisted of using the SLs to direct instruction and data words to the function units, which could be hooked to other function units in a pipeline, along with other pipelines in parallel. A separate set of eight ROMs could be used for data. It took until to declassify a paper on the design. Although impressively elegant, it probably didn't warrant that length of secrecy. It also featured an innovative feature to add custom instructions to the CPU. It included a 4-bit accumulator, 4-bit Y register and 2 or 3-bit X register, which combined to create a 6 or 7 bit index register for the 64 or nybbles of on chip RAM. A 1-bit status register was used for various purposes in different contexts. There was also a 6-bit subroutine return register and 4-bit page buffer, used as the destination on a branch, or exchanged with the PC and page registers for a subroutine amounting to a 1-element stack, branches could not be performed within a subroutine. An interesting feature of the PC is it was incremented using a feedback shift register, not a counter, so instructions were not consecutive in memory, but since all memory was internal, this was not a problem. Instructions were 8 bits with twelve hardwired, and with a 31X16 element PLA allowing 31 custom microprogrammed instructions. All hardwired instructions were single cycle, and no interrupts were allowed. The was the successor to the Aprilintended as a terminal controller, and similar to the While the had 14 bit PC and addressing, the had a 16 bit address bus and an 8 bit data bus. Internally it had seven 8 bit registers A-E, H, L - pairs BC, DE and HL could be combined as 16 bit registersa 16 bit stack pointer to memory which replaced the 8 level internal stack of theand a 16 bit program counter.
MOS Technology 6502